1. Field of the Invention
The invention relates to a wrong operation preventing circuit in semiconductor unit, used for preventing data destruction of semiconductor memory and the like from happening.
2. Related Background Art
In semiconductor unit, for example, microcomputer with one chip, internal circuit is operated according to the input of clock signal with high frequency. Such clock signal, however, changes due to some reason, thereby, when its frequency rises over a definite upper limit value, the internal circuit will occurs wrong operation. By such wrong operation, some trouble will happen, for example, either data stored in the internal circuit will be destroyed, or secret information will be stolen. In order to prevent such trouble from happening, in the past, the following wrong operation preventing circuit is used.
FIG. 8 is a structure diagram of conventional wrong operation preventing circuit.
The conventional wrong operation preventing circuit is exclusively installed within semiconductor unit, and comprises mutually connecting both of a high area passing circuit 101 and a amplifying circuit 102 as shown by FIG. 8(a).
The high area passing circuit 101, as shown by FIG. 8(b), is formed from condenser 111 and resistance 112; its input terminal is connected with clock signal line. The amplifying circuit 112, as shown by FIG. 8(c), is formed from two inverters 113, 113; its output terminal is connected with central processing unit (CPU) 103.
In such wrong operation preventing circuit, when the frequency of clock signal rose over a definite value i.e. predetermined upper limit value, the high area passing circuit 101 outputs a xe2x80x9cHxe2x80x9d signal, then, the amplifying circuit 102 amplifies the xe2x80x9cHxe2x80x9d signal and output a xe2x80x9cHFCLKxe2x80x9d signal to the CPU 103. Thus, the CPU 103 is reset.
But, in semiconductor unit, with respect to the occurrence of wrong operation, not only being because of the rising of clock signal, but also being because of that, for example, the rising of temperature in itself due to access time for memory. Thereby, in the latter case, for example, such structure is used, which is disclosed by patent document of Japan patent publication No. 10-326125. That is, using a temperature sensor to measure the temperature of semiconductor unit, if the temperature is over predetermined temperature, then using a cooling fan to cool the semiconductor unit.
However, on the one hand, with respect to the plural of semiconductor units with mass production, their clock signal frequencies capable of normally operating i.e. the upper limit value of operating frequencies are different from each other. On the other hand, in the conventional wrong operation preventing circuit as stated above, such structure to output a reset signal only based on unique predetermined upper limit value is supplied. Thus, for applying in common such structure to all semiconductor units, it is necessary to respectively set such an upper limit value as predetermined upper limit value that is corresponding to a semiconductor unit whose upper limit value of operating frequency is smallest, in all semiconductor units.
Because of this, with respect to such semiconductor unit whose upper limit value of operating frequency is bigger, sometime, its CPU will be reset even if do not need to be reset. Therefore, such problem as that the decline of processing efficiency of semiconductor unit existed.
Further, as stated above, in such case that using a cooling device described by above mentioned patent document to solve the rising of temperature, semiconductor unit will become big and expensive.
Thus, in the prior art, such above stated problems to be solved was left.
To solve the conventional problems as mentioned above, the following structures are used.
According to the invention, there is provided a wrong operation preventing circuit for preventing the wrong operation of semiconductor unit including memory and CPU from happening, comprising:
a detection use memory cell section serving as a judgement object of the wrong operation, which is installed at the memory and is formed from at least one memory cell;
a bit line which is connected with the detection use memory cell section and is added by pre-charge voltage synchronizing with clock signal;
a voltage detection section for detecting the dropping of the pre-charge voltage added on the bit line;
a operation judgement section which outputs a reset signal to the CPU when the dropping voltage detected by the voltage detection section is bigger than a predetermined value.
In the wrong operation preventing circuit, the detection use memory cell section may be any one of memory cell portions used for forming the memory.
Also, the detection use memory cell section may be a memory cell portion newly formed at the memory for detection exclusive use.
Further, in the wrong operation preventing circuit, the bit line may have a longest length than other bit lines connected with the memory.
Also, the bit line may have a delay element.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.